System LSI Design Education Program Promoted by STARC

Design for MOSIS Education Program

Microelectronic design cooperative education program

We describe our experiences in using microelectronic design projects as cooperative education experiences for electrical engineering majors. We discuss funding of the necessary VLSI design laboratory and describe our course offerings. We believe our “alternative co-op” program is of value to VLSI educators with limited resources who are looking for ways to provide students with an alternative t...

System LSI: Challenges and Opportunities

What will happen if we continue to scale a CMOS device? Gate controllability will be degraded. If gate oxide thickness is kept constant in order to suppress gate leakage, and if channel length is scaled further, potential of silicon surface near the source that is associated with VTH is lowered by depletion layer capacitance of the drain (CD), as well as gate capacitance (CG). When CD is not sm...

LSI Design Flow Development for Advanced Technology

LSIs that adopt advanced technologies, as represented by imaging LSIs, now contain 30 million or more logic gates and the scale is beginning to approach the level of 100 million gates. As compared with the 90 nm process generation, this is three to ten times the number of gates. With advanced technologies such as 40 nm and 28 nm, the process characteristics become remarkably complex and wiring ...

System LSI Development Is Changing ! R & D of the high - level design automation system “ CyberWorkBench ”

Dr. Kazutoshi WAKABAYASHI Senior Manager System Devices Research Laboratories We are sometimes astonished by the recent advances in cellular phones and digital home appliances that feature a wide range of new capabilities. These advances are supported by the system LSI technology, which integrates a large number of functions on a single chip. However, as the advances have also increased the bur...